1. Field of the Invention
The invention relates to a process for manufacturing a semiconductor device, and more particularly to a process for manufacturing a field effect transistor of insulating gate type comprising a structure including Source and Drain regions of high carrier density and a separate region of low carrier density adjoining to the source and drain regions for mitigating the field effect.
2. Description of the Related Art
The insulating gate type of field effect transistor broadly used now in semiconductor integrated circuits has a steep electric field along channel regions due to the trend of subminiaturization of devices. It is a problem that hot carrier generated by the steep electric field deteriorates properties of devices. The problem may be solved by the so-called lightly doped drain structure (LDD) which is provided with a separate region of low carrier density between source and drain regions of high carrier density and channel region under gate electrode in order to mitigate concentration of electric field on and near the boundary of the channel region and drain region subjected to high voltage. The LDD structure has yet a problem of drop of drive current since the low carrier density region behaves as parasitic resistance. The low carrier density region may be modified and formed, as proposed in Japanese Unexamined Patent Publication No. Hei 2-226726 (1990) or Hei 3-104125 (1991), by overlapping the gate and drain regions and making use of difference of film thickness with inverted T-shaped gate electrode (reference '726) or providing a provisional gate (reference '125).
It is rather difficult in the first reference to control work for the inverted T-shaped gate electrode. Also, the second reference which includes a forming process of the provisional gate requires plural times of photolithographic process, leading to an increase of the total number of specific processes.